An integrated circuit may include at least one functional circuit which operates in response to a clock signal. A clock distribution tree may be provided to distribute the clock signal to the functional circuit. The clock signal drives high capacitance wires in the clock distribution tree, and so the clock distribution tree tends to consume a relatively large amount of power. The higher the clock frequency, the more often the clock signal switches between low and high states and so the greater the amount of power consumed by the clock distribution tree. If a lower frequency clock signal was used, then power could be conserved, although this would limit the functionality and performance level achieved by the functional circuit.
Functional circuits usually operate in response to the rising edge of the clock signal. It has been proposed to modify the configuration of a functional circuit so that it responds to both rising and falling edges of the clock signal. Hence, the existing performance level could be achieved with a clock signal having half the frequency. However, many existing circuit designs are designed to operate in response to only the rising edges, so are not compatible with this technique. In an integrated circuit comprising hundreds of functional circuits, modifying each functional circuit to change the way in which it responds to the clock signal may require considerable design and manufacturing expenditure. The present technique seeks to reduce the power consumed in distributing a clock signal in a way that enables existing functional circuits to be used whilst still maintaining the existing functionality and performance level of the functional circuits.